The present invention relates to sigma delta (ΣΔ) converters.
In conventional ΣΔ converters, a front-end stage samples an input voltage with charge storage components (i.e., storage capacitors), and the charge is then accumulated on another set of components (i.e., integrating capacitors). The integrated samples are then quantized by an analog-to-digital converter (ADC), for example, a flash ADC. The ADC output is also looped back via a feedback DAC to be subtracted from the input voltage. The feedback DAC samples a reference voltage dependent on the ADC output bit state(s).
FIG. 1 illustrates a conventional single phase switched capacitor integrator that can be provided in a ΣΔ front-end stage with an associated operation timing diagram. In FIG. 1, the input voltage Vx (or −Vx depending on input capacitor polarity), where Vx=Vx+−Vx−, is sampled onto input capacitors Cina and Cinb based on timing signals φ1 and φ2. The left hand side (LHS) switches are controlled by timing signals φ1 and φ2, while the right hand side (RHS) switches are controlled by φ1r and φ2r. The two sets of timing signals generally have the same phase relationship; however, the rising and falling edges may be slightly different to minimize undesirable effects, such as charge injection. The details of the slight differences are not described here. The above circuit is sampled at frequency fs, and Vs is a supply voltage. The timing signals φ1 and φ2 alternate and, hence, their respective rising and falling edges are substantially synchronized. Thus, the average current drawn from nodes Vx+ and Vx− occurs as follows: IVx+= −IVx−=2VxfsCin,  Eq. 1where Cin=Cina=Cinb. The average current drawn varies based on the content of the input signal because the average current will flow from the node with higher potential into the node with lower potential and is not altered by the amount charge transferred to the output of the circuit. Simply stated, the average current drawn is a function of Vx, fs, and Cin.
FIG. 2 illustrates a conventional single phase-switched capacitor integrator that can be provided in a ΣΔ feedback DAC with an associated operation timing diagram. In FIG. 2, a reference voltage Vref, where Vref=Vref+−Vref−, is sampled onto input capacitors Crefa and Crefb based on timing signals φ1 and φ2, which are modulated by an information signal (y(n)). The LHS switches have control inputs coupled to timing signals φ1 and φ2, while the RHS switches are controlled by φ1r and φ2r. The two sets of timing signals generally have the same phase relationship as illustrated; however, the rising and falling edges may be slightly different to minimize undesirable effects such as charge injection. The details of the slight differences are not described here. The above circuit is sampled at frequency fs. The timing signals φ1 and φ2 alternate and, hence, their respective rising and falling edges are substantially synchronized. Also, the LHS switches are controlled by the state of a previous output stage y(n). Thus, the average current drawn by the circuit can be expressed as:
                                          I                          Vref              ⁢                                                          +                                _                =                                            -                              I                                  Vref                  ⁢                                                                          -                                                      _                    =                                    2              ⁢                                                          ⁢                              V                ref                            ⁢                              f                s                            ⁢                              C                ref                                      -                                          1                2                            ⁢                              V                ref                            ⁢                              f                s                            ⁢                              C                ref                            ⁢                                                                                    y                    ⁡                                          (                      n                      )                                                        -                                      y                    ⁡                                          (                                              n                        -                        1                                            )                                                                                                                                              Eq        .                                  ⁢        2            Here, the LHS feedback introduces a dependency between the current drawn from the reference voltage and a state of a previous output stage y(n). Hence, any series impedance on the reference nodes can cause non-linear modulation of the effective reference voltage, inducing tonal behavior, which distorts the output signal.
Accordingly, the inventors perceive a need in the art for ΣΔ structure having input circuits that conserve current consumption, whose current draw is not dependent on variation in input signal and that delivers outputs with greater accuracy than prior systems.